1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device including a MOS field-effect transistor.
2. Description of the Background Art
In a MOS field-effect transistor formed on the surface of a silicon substrate, the interval between source/drain regions is generally reduced following refinement of the device, to easily result in punch through. In order to suppress such punch through, the impurity concentration of a channel region must be increased. When the impurity concentration of the channel region is increased, however, not only the probability of Coulomb scattering resulting from impurities is increased but also the thickness of an inversion layer is more reduced, and hence electrons flowing through the channel region are easily influenced by interfacial scattering on the interface between a gate insulator film and the silicon substrate.
More specifically, electrons are easily jammed to the gate insulator film due to a gate electric field when the thickness of the inversion layer is more reduced, to inconveniently resulting in reduction of electron mobility. A MOS field-effect transistor having an SOI (silicon on insulator) structure is expected as an exemplary countermeasure against such inconvenience. In the MOS field-effect transistor having an SOI structure, the thickness of a silicon layer formed with a channel region is so reduced as to suppress punch through, whereby the impurity concentration of the channel region can be reduced. Thus, the silicon layer can be easily controlled with a gate electric field. Therefore, the gate electric field can be so reduced as to reduce the probability of jamming electrons to a gate insulator film on the interface between the gate insulator film and the silicon layer. Thus, influence by interfacial scattering as well as Coulomb scattering resulting from impurities can be so reduced that electron mobility can be increased in the MOS field-effect transistor having an SOI structure.
In relation to the SOI structure, source/drain regions lifted up in an elevated structure are generally proposed in order to reduce the resistance of the source/drain regions. Such an elevated structure for source/drain regions is disclosed in “Transistor Elements for 30 nm Physical Gate Length and Beyond”, Intel Technology Journal, Vol. 06, May 16, 2002, ISSN1535766X, pp. 42–54, for example. According to the structure disclosed in this literature, portions of source/drain regions of a silicon layer serving as an active layer in an SOI structure are lifted up so that the thickness of the source/drain regions of the silicon layer is larger than that of a channel region. Thus, the thickness of the source/drain regions can be increased while reducing that of the channel region, whereby the resistance of the source/drain regions can be reduced while improving electron mobility. According to the structure disclosed in the aforementioned literature, further, a gate electrode consisting of a polysilicon film is formed on the channel region through a gate insulator film consisting of a high dielectric constant insulator film.
In a MOS field-effect transistor of the SOI structure including the source/drain regions elevated in the elevated structure disclosed in the aforementioned literature, however, the gate electrode formed by the polysilicon film is inconveniently depleted in the vicinity of the gate insulator film. When the polysilicon film is depleted in the vicinity of the gate insulator film, the effective thickness of the gate insulator film is increased to disadvantageously deteriorate the device performance.
The gate electrode consisting of the polysilicon film may conceivably be replaced with a gate electrode consisting of a metal. When such a gate electrode (metal gate) consisting of a metal is employed, no metal is depleted in the vicinity of the gate insulator film and hence the effective thickness of the gate insulator film is not increased.
When the gate electrode is made of a metal, however, the Fermi level of the metal is pinned on the interface between the metal gate electrode and the gate insulator film, disadvantageously leading to difficulty in controlling a threshold voltage with a low voltage.